1. Field of the Invention
The present invention relates to a failure analyzing system and a method for displaying a failure. More particularly, the present invention relates to a failure analyzing system and a method for displaying a failure that can display a position of a failure in a semiconductor device.
2. Description of the Related Art
ATPG (Auto Test Pattern Generation) generates a test program and a pattern program for testing a semiconductor device and supplies them to a semiconductor test device. The semiconductor test device tests the semiconductor device with the test program and the pattern program that were generated by the ATPG, and outputs failure data to the ATPG as a result of the test. The ATPG then detects a defective circuit existing in that semiconductor device based on the failure data output from the semiconductor test device and generates a list of possible defective circuits.
Moreover, the ATPG further generates a test program and a pattern program for testing the defective circuit existing in the semiconductor device in detail based on the list of possible defective circuits generated by the failure data. By making the semiconductor test device execute a detailed test for the semiconductor device, the defective circuits in the semiconductor device are narrowed down.
According to the ATPG and semiconductor test device described above, the defective circuit in the semiconductor device can be determined. However, it is not possible to determine commonality or tendency of positions of failures between semiconductor devices or a plurality of plates of wafer each having a plurality of semiconductor devices formed thereon. Therefore, it is difficult to identify the cause of the defective circuit in the semiconductor device.